1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an improved process of forming a shallow trench isolation structure with enhanced field dielectric characteristics and preservation of active area sidewall. The shallow trench isolation structure may further comprise an improved capacitor structure. The field dielectric and capacitor structure are formed by conversion of a deposited polycrystalline layer deposited within a trench formed by a shallow trench processing sequence.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are interconnected by a conductor which extends over a dielectric which separates or "isolates" those devices. Implementing an electrical path across a monolithic integrated circuit thereby involves selectively connecting isolated devices. When fabricating integrated circuits it must therefore be possible to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for an MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS processing involves oxidizing field regions between devices. The oxide grown in field regions are termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS. First, a growing field oxide extends laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topographical disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the "shallow trench process". Despite advances made to decrease bird's-beak, channel-stop encroachment and non-planarity, it appears that LOCOS technology is still inadequate for submicron MOS technologies. The shallow trench process is better suited for isolating densely spaced active devices having field regions less than one micron in lateral dimension.
Conventional trench processes involve the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. Some trench processes include an interim step of growing oxide on trench walls prior to the trench being filled with a deposited dielectric. After the trench is filled, it is then planarized to complete the isolation structure.
The trench process eliminates bird's-beak and channel-stop dopant redistribution problems. In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface. Still further, field-oxide thinning in narrow isolation spaces does not occur and the threshold voltage is constant as a function of channel width.
While the conventional trench isolation process has many advantages over LOCOS, it is generally recognized that deposited oxide used to fill the trench is of a lower dielectric quality than thermally grown field oxide used in LOCOS processing. Deposited dielectrics, such as CVD SiO.sub.2, are generally less dense than thermally grown oxides and have an altered stoichiometry that can cause changes in the mechanical and electrical properties of the film. Thermally grown oxide, on the other hand, has a generally uniform stoichiometry arranged for consistent electrical isolation micro and macroscopically across the dielectric structure. If oxide is thermally grown on the isolation trenches however, silicon at the periphery of the trench is consumed and the isolation structure encroaches on the active area (similar to the manner in which the bird's beak encroaches the active area in a conventional LOCOS process). It would be desirable to combine the advantages obtained by using a thermal oxide as an isolation structure with the advantages afforded by trench processing.
In addition, LOCOS and conventional trench isolation processes also present problems associated with the fabrication of discrete capacitors. Many semiconductor devices, such as those used in telecommunication products, require capacitors to handle various analog signals. For example, switching of carefully sized capacitors is necessary to accurately sample an analog signal. Modulators which use switch capacitor structures, i.e., delta sigma modulators rely upon carefully controlled capacitor structure to accurately sample an incoming analog signal. Modems, codecs, analog filters, and quantizers also rely upon the integrity of the capacitor structure. Processes designed primarily for fabricating transistors and interconnects for high speed digital applications are less than ideally suited for manufacturing passive circuit elements. It is not uncommon in such processes, for example, to produce capacitors by arranging a dielectric between first and second metal levels or between a metal level and a substrate. Controlling the capacitance of these structures is difficult due to variations in the inter-level dielectrics caused by multi-layered dielectric structures and multiple planarization steps.
In addition, the thickness of the dielectric between the "plates" of metal-to-metal and metal-to-substrate capacitors requires large area structures to obtain an adequate capacitor in many applications. Dielectric thickness must by quite small in many precision capacitor applications, yet there is a tendency to increase the interlevel dielectric thickness to reduce unwanted capacitive coupling between, for example, interconnect lines carrying digital signals. Thus, it is often difficult to merge the benefits of digital circuitry with analog circuits often attributed to telecommunication applications.
Capacitance C of a parallel plate structure is given by: EQU C=.kappa..epsilon..sub.0 A/d (Eq. 1)
where .kappa. is the dielectric constant (approximately 3.9 for SiO.sub.2), .epsilon..sub.0 is the permittivity constant (8.9.times.10.sup.-12 C.sup.2 /N-m.sup.2), d is the distance between the plates, and A is the cross-sectional area of the structure, it is seen that: EQU A=dC/.kappa..epsilon..sub.0 (Eq. 2)
Thus, a 1.0 picofarad capacitor using a metal-to-metal structure with an 0.8 micron SiO.sub.2 interlevel dielectric would require a cross sectional area of approximately 23,000 square microns. The capacitor area can represent a significant percentage of the device's entire area. While reducing the interlevel dielectric thickness would reduce the area required to produce a given discrete capacitor, it would also increase unwanted capacitive coupling between interconnects on the first level and interconnects on the second level. As device geometries have continued to shrink, capacitive coupling effects have become more significant in determining the speed at which the device may be operated. Consequently, an industry trend is to increase the thickness of interlevel dielectrics to combat undesirable parasitic capacitance--opposite that which may be needed for producing a small analog sampling capacitor. From equation 2, increased dielectric thickness requires an even larger area capacitor.
It would therefore be desirable to implement a method to produce discrete capacitors requiring less cross-sectional area than discrete capacitors produced from conventional LOCOS and trench processes. It would also be desirable to implement a method to produce discrete capacitors having a capacitance that is independent of the metal-to-substrate dielectric and the metal-to-metal dielectric thickness.